Traditional testing methodologies of processor or logic semiconductor chips containing SRAM macros with redundant elements for failure relief include Array Built In Self Test (ABIST), and external test support equipment and data processing. These methods involve collection of data from the memory arrays regarding failing locations and some form of on chip fuse and/or latch structures to control the invocations of spare or redundant elements within the memory array elements for failure relief. This is sufficient when the redundant element circuitry performs a straightforward replacement of the defective elements with the memory array structure, enabling the spare elements to become active when a compare of the defective location address to the incoming address to the memory array is favorable.
Subsequent testing of the processor or logic semiconductor chip(s) containing SRAM macros with redundant elements. Further failure relief can be accommodated as long as the fuse or latch elements used for control of the redundant elements can be appended to, and thus provide further failure relief within the memory array structure. That is the case until the available number of repairable elements is exhausted, or at the point that the fuse or latch elements may no longer be appended or updated. This may occur with laser blown fuse elements later in the test and assembly process.
Another type of redundancy involves “skip over” redundant element techniques. In this case the spare element is no longer substituted for the defective element, but instead a spare is introduced and all replaceable elements internal to the memory array structure are shifted until the defective element is reached and no longer used. Traditional methodologies for test, fail detection and replacement can be used for “skip over” redundant elements if the replaceable elements are restricted to a single repairable element, or repair action within the memory array structure. The difficulty encountered at this point is in further data collection of subsequent levels of assembly test, where one must know if the redundant elements were invoked, to properly calculate internal memory array locations of subsequent fails. i.e. were the observed fails shifted from their base positions by the presence of a repair within the memory array.
A more general case is the provision to support multiple repairable elements (or spares) within the memory array. This provides techniques for the practical capability of multiple ‘skip over’ redundant or repairable memory array elements for SRAM macros. The problem created here, in terms of multiple levels of test and data collection for purposes of failure relief within the SRAM memory array elements, requires not only maintenance of a fail history of the device under test, but a maintenance of the redundancy configuration of the memory array at the time of that data collection or test point. This collected data must then be further analyzed and adjusted based on the repair configuration at the time of test, and precisely known at all levels of assembly test and data collection.
The support for two dimensional redundancy allocation is growing more complex for SRAM memory arrays with increased data 10 widths (number of data bits into and out of the array) and the increased number of repair actions desired for yield improvement on high speed, high density SRAM products.
In addition, redundant elements in the SRAM macros are not restricted to just the address or data bit dimensions, but are now becoming increasingly a portion of the column addressing and data bit architecture of the SRAM. The thrust here has been to keep the size of the redundant element as small as possible for low overhead and high area efficiency, while increasing the overall number of repair actions available for failure relief of the memory array.
Therefore, it is becoming increasingly important to determine with more specificity where a failure has occurred in a memory array, for subsequent processing and generation of a failure relief condition of the memory array. In addition it is now an issue to know specifically the configuration of the memory array in terms of the redundant element configurations, for subsequent levels of test and data collection for failure relief within the memory array.
Another aspect of test of SRAM memory arrays with redundancy is the actual test of the redundant elements themselves. Traditional test and repair processes rely on a subsequent level of assembly test to provide test coverage of the elements used to provide failure relief within the memory array. This poses a concern if the test environments are sufficiently different to allow potential AOQL (average outgoing quality level) degradation for the repaired configurations, if subsequent levels of test to determine the original failures are not sufficiently repeated on the repaired configuration. Also, there is a producer cost risk associated with continued processing of a die that is not guaranteed to function at expected levels until late in the manufacturing process
With increased levels of integration and scaling driving significant increases in the number of memory bits on a high performance processor chip, and significant development in using redundant elements to provide failure relief at all levels of assembly test in addition to initial fabrication test, it is becoming more important to provide efficient low cost test of redundant elements in addition to the main memory array fabrication tests.
A clear need exists to reduce the complexity of the data collection and process to establish continued repairable configurations of a memory array with redundant elements, and thereby reduce the test time and cost required.
There is also a clear need to reduce the overhead of the test data and processing for establishment of the redundant element configuration for failure relief of memory arrays with redundant circuits.